1. Field of the Invention
The present invention generally relates to radio equipment for transmitting a digital signal and its peripheral apparatus, and more particularly, to radio equipment and its peripheral apparatus for suppressing interference to a radio signal which is generated by the digital signal.
2. Description of the Related Art
Recently, a variety of radio communication systems such as a portable telephone service system are developing and a wide range of radio frequencies are used for the systems. For such a system using a wide range of radio frequencies, a digital modulation method capable of achieving higher usage efficiency of the frequencies is being used instead of an analog modulation method. For example, portable telephone service systems operating at the 800-MHz band and 1.5-GHz band are already in commercial use by the digital modulation method of .pi./4-shifted quadrature phase shift keying (QPSK).
Further, transmission rate and processing speed of the digital signal also increase according to development of LSI technologies. Therefore, frequencies of a timing clock of the digital signal and a clock for processing the digital signal increases close to a carrier frequency for radio transmission.
Since the digital signal and the clock signal are formed by rectangular waves, these signals have a number of high-order harmonic components. Frequencies of the harmonic components are spread to UHF and VHF bands. Therefore, when the frequencies of the harmonic components are present in a receiving frequency band of a radio signal, the harmonic components enter a receiving circuit of radio equipment as interference and have influence on a desired signal. The harmonic components are obtained by Fourier-expanding a digital signal k(t) as follows: ##EQU1## According to the above equation, the harmonic components have odd-order frequency components.
In general, to miniaturize size of the radio equipment, radio parts and digital signal processing parts are arranged close to each other in the same housing. To improve transmission quality and to reduce power consumption, a highly-sensitive receiver has also been developed. Therefore, in such a configuration, the above-mentioned interference due to harmonics may cause a larger problem.
In Japanese Laid-Open Patent Applications No.3-255510 and No.5-90987, methods of frequency-modulating a clock signal of a clock oscillator for a control circuit such as a CPU are disclosed. By the frequency modulation, the spectrum of harmonics of the clock signal is spread, and levels of high-order harmonics may be reduced. Therefore, interference to a receiving circuit may also be reduced. More specifically, Japanese Laid-Open Patent Application No.5-90987 shows an embodiment in which the above-mentioned method is applied to radio equipment using an analog modulation and demodulation method.
However, in radio equipment using a digital modulation and demodulation method, a digital signal such as transmission data as well as the clock oscillator of the control circuit also generates high-order harmonics. When increasing frequency deviation of the modulation of the clock signal in the control circuit to further reduce the level of the harmonics of the clock signal, an error may occur in an operation of the control circuit. Furthermore, the clock frequency is increasing, and the high-order harmonics may easily have influence on the radio signal.
FIG. 1 shows a block diagram of typical digital radio equipment. The equipment 1 shown in FIG. 1 includes a transmission part and a reception part. The transmission part comprises a data processing circuit 2, a modulator 4, and a transmitting circuit 6. The reception part comprises a receiving circuit 8, a demodulator 10, and a data processing circuit 12. The data processing circuit 2 includes a speech CODEC 16 and a signal processing circuit 18. The data processing circuit 12 includes a signal processing circuit 20 and a speech CODEC 22.
In the speech CODEC 16, a speech signal is converted to digital data based on a timing clock from a clock oscillator 30. In the signal processing circuit 18, the digital data is formatted in a format suitable for being transmitted. For example, when the radio equipment 1 operates in a time division multiple (TDM) system, the digital data is distributed to TDM frames. When the modulation method is QPSK, the digital data is separated to an I (in-phase) channel signal and a Q (quadrature phase) channel signal.
In the modulator 4, the digital data processed in the signal processing circuit 18 is filtered, and a first local signal is digitally modulated by the filtered digital data. For the digital modulation, phase modulation such as QPSK and frequency modulation such as GMSK are usable. An output signal of the modulator 4 is converted to a radio signal by the transmitting circuit 6, and is transmitted through a filter 40 to an antenna 42.
A radio signal which has come through the antenna 42 and the filter 40 is received in the receiving circuit 8, and is converted to an intermediate frequency signal. The intermediate frequency signal is demodulated in the demodulator 10 to reproduce digital data at a baseband frequency. The reproduced digital data is processed to digital data including a timing clock for the speech CODEC 22 in the signal processing circuit 20, and is converted to a speech signal in the speech CODEC 22.
The speech CODECs 16, 22 and the signal processing circuits 18, 20 may be commonly constructed with a digital signal processor (DSP). Timing clocks from the clock oscillator 30 are provided to the speech CODECs 16, 22, and DSP clocks from the clock oscillator 32 are provided to the signal processing circuits 18, 20. The speech CODECs 16, 22 and the signal processing circuits 18, 20 are connected to CPU 14 operable with a CPU clock provided from a clock oscillator 34 through a bus line.
In such a circuit configuration, the digital data is generated based on the timing clock for the speech CODEC and is formed by the rectangular waves. Therefore, the digital data includes a number of high-order harmonic components. When a frequency of one of the high-order harmonic components is close to the radio channel frequency, the harmonic component shown in a dotted line (A) may cause interference during operation of the receiving circuit 8.
The clock oscillators 30, 32 which generate the timing clock and the DSP clock for generating and processing the digital data have respectively high-frequency clock sources. Therefore, the high-frequency clock sources also generate high-order harmonic components which influence the receiving circuit 8. The interference is shown in dotted lines (B) and (C).
Further, the demodulator 10 commonly has a clock recovery circuit for recovering a timing clock to reproduce the baseband signal. Therefore, the clock recovery circuit and the reproduced baseband signal also generate high-order harmonic components which influence the receiving circuit 8. The interference is shown in a dotted line (D).
The CPU clock operating the CPU 14 and input and output data flowing through the bus line also generate high-order harmonic components which may cause interference. The interference is shown in dotted lines (E) and (F).
Still further, peripheral apparatuses such as a personal computer, a facsimile, a television, a radio, and a global positioning system (GPS), which are located close to the digital radio equipment 1, also have many clock oscillators. Therefore, harmonics are generated from those clock oscillators and harmonics are also generated from digital signals transmitting through cables which connect the peripheral apparatuses. These harmonics also influence the receiving circuit 8 of the digital radio equipment 1 as interference is shown in dotted lines (G) and (H).
Next, a detail description will be given of the interference by the timing clock generated in clock oscillator 30.
For example, when a bit rate of the timing clock is 11.2 kbps, the clock oscillator 30 has a 2.688-MHz clock source, and a signal divided by 24 is used as the timing clock. In this case, a 163-order harmonic of an output of the 2.688-MHz clock source is a 438.144-MHz signal. If a radio channel is used at a frequency of 438.150 MHz, the harmonic frequency is close to the radio channel frequency. The harmonic may interfere with the radio channel being received.
FIG. 2A and FIG. 2B show signal space diagrams when a QPSK signal is received with interference. FIG. 2A shows the signal space diagram at an instant of time, and FIG. 2B shows the signal space diagram averaged over a given time period. When the high-order harmonic component of the clock is added to an ideal QPSK signal, as shown in FIG. 2A, four ideal signal points of the QPSK signal are shifted by interference in the same direction. However, the shifted direction rotates about each signal point according to a frequency difference between the radio channel and the interference (in the previous example, 6 kHz). As a result, as shown in FIG. 2B, in averaging over the given time period, the four ideal signal points respectively spread in a circle form. The interference becomes a bright-line interference. When a size of the circle exceeds a decision level, an error occurs.
As mentioned above, in conventional digital radio equipment, since the data is formed by the digitally-shaped clock, the harmonics are generated from the digital data and the clock. Namely, the interference which did not occur in analog radio equipment is newly generated for the receiving circuit in digital radio equipment.
Further, for improving frequency utility and services, the data transmission speed needs to be increased. For this requirement, the clock sources of the clock oscillator for generating the timing clock and the DSP oscillator for processing the digital data tends to have a higher frequency. On the other hand, in a relatively low radio frequency, the digital modulation and demodulation methods are being used. Therefore, a level of interference due to the harmonics of the clock used for the digital data increases, and the interference may strongly influence the radio receiving circuit.